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Nanopackaging of Si(100)H wafer for atomic-scale investigations

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Nanopackaging of Si(100)H wafer for atomic-scale investigations

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dc.contributor.author Sordes, Delphine pl
dc.contributor.author Thuaire, Aurélie pl
dc.contributor.author Reynaud, Patrick pl
dc.contributor.author Rauer, Caroline pl
dc.contributor.author Hartmann, Jean-Michel pl
dc.contributor.author Moriceau, Hubert pl
dc.contributor.author Rolland, Emmanuel pl
dc.contributor.author Kolmer, Marek [SAP13036853] pl
dc.contributor.author Szymoński, Marek [SAP11006649] pl
dc.contributor.author Durand, Corentin pl
dc.contributor.author Joachim, Christian pl
dc.contributor.author Chéramy, Séverine pl
dc.contributor.author Baillin, Xavier pl
dc.contributor.editor Kolmer, Marek [SAP13036853] pl
dc.contributor.editor Joachim, Christian pl
dc.date.accessioned 2018-01-10T13:04:44Z
dc.date.available 2018-01-10T13:04:44Z
dc.date.issued 2017 pl
dc.identifier.isbn 978-3-319-51846-6 pl
dc.identifier.uri https://ruj.uj.edu.pl/xmlui/handle/item/48394
dc.language eng pl
dc.rights Dodaję tylko opis bibliograficzny *
dc.rights.uri *
dc.title Nanopackaging of Si(100)H wafer for atomic-scale investigations pl
dc.type BookSection pl
dc.pubinfo Cham : Springer pl
dc.description.physical 25-51 pl
dc.abstract.en Ultra-high vacuum (UHV) investigations have demonstrated a successful development of atomic nanostructures. The scanning tunneling microscope (STM) provides surface study at the atomic scale. However, the surface preparation is a crucial experimental step and requires a complex protocol conducted in situ in a UHV chamber. Surface contamination, atomic roughness, and defect density must be controlled in order to ensure the reliability of advanced UHV experiments. Consequently, a packaging for nanoscale devices has been developed in a microelectronic clean room environment enabling the particle density and contaminant concentration control. This nanopackaging solution is proposed in order to obtain a Si(001)-(2$\times$ 1):H reconstructed surface. This surface is protected by a temporary silicon cap. The nanopackaging process consists in a direct bonding of two passivated silicon surfaces and is followed by a wafer dicing step into 1-cm2 dies. Samples can be stored, shipped, and in situ opened without any additional treatment. A specific procedure has been developed in order to open the nanopackaged samples in a UHV debonder, mounted in the load-lock chamber of a low-temperature STM system (LT-STM). Statistical large scan LT-UHV-SEM images and LT-UHV-STM images have been obtained enabling the surface study at the atomic resolution. pl
dc.description.series Advances in Atom and Single Molecule Machines, ISSN 2193-9691, eISSN 2193-9705 pl
dc.description.publication 1,7 pl
dc.description.conftype international pl
dc.identifier.doi 10.1007/978-3-319-51847-3_2 pl
dc.identifier.eisbn 978-3-319-51847-3 pl
dc.title.container On-Surface atomic wires and logic gates : updated in 2016 proceedings of the International Workshop on Atomic Wires, Krakow, September 2014 pl
dc.language.container eng pl
dc.affiliation Wydział Fizyki, Astronomii i Informatyki Stosowanej : Instytut Fizyki im. Mariana Smoluchowskiego pl
dc.subtype ConferenceProceedings pl
dc.conference International Workshop on Atomic Wires; 2014-09-10; 2014-09-12; Kraków; Polska; indeksowana w Web of Science; ; ; pl
dc.rights.original bez licencji pl
dc.sourceinfo liczba autorów 29; liczba stron 193; liczba arkuszy wydawniczych 13; pl
dc.publisher.ministerial Springer pl


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