Sampling FEE and trigger-less DAQ for the J-PET scanner

doi:10.5506/APhysPolB.47.491

Sampling FEE and trigger-less DAQ for the J-PET scanner

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Sampling FEE and trigger-less DAQ for the J-PET scanner

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punktacja MEiN [2016 A]: 20

title:	Sampling FEE and trigger-less DAQ for the J-PET scanner
author:	Korcyl Grzegorz , Alfs Dominika, Bednarski Tomasz , Białas Piotr , Czerwiński Eryk , Dulski Kamil, Gajos Aleksander , Głowacz Bartosz , Jasińska B., Kisielewska Daria , Kapłon Łukasz , Kowalski P., Kozik Tomasz , Krzemień Wojciech , Kubicz Ewelina , Mohammed Muhsin , Niedźwiecki Szymon , Pałka Marek , Pawlik-Niedźwiecka Monika , Raczyński L., Rudy Zbigniew , Rundel Oleksandr , Gupta-Sharma Neha , Silarski Michał , Słomski Artur , Stoła Karol, Strzelecki Adam , Wieczorek Anna , Wiślicki W., Zgardzińska B. K., Zieliński Marcin , Moskal Paweł
journal title:	Acta Physica Polonica. B
volume:	47
issue:	2
date of publication :	2016
pages:	491-496
ISSN:	0587-4254
eISSN:	1509-5770
DOI:	10.5506/APhysPolB.47.491
notes:	Autorka Daria Kisielewska podpisana jako Daria Kamińska.
language:	English
journal language:	English
abstract in English:	In this paper, we present a complete Data Acquisition System (DAQ) together with the readout mechanisms for the J-PET tomography scanner. In general, detector readout chain is constructed out of Front-End Electronics (FEE) measurement devices such as Time-to-Digital or Analog-to-Digital Converters (TDCs or ADCs), data collectors and storage. We have developed a system capable for maintaining continuous readout of digitized data without preliminary selection. Such operation mode results in up to 8 Gbps data stream, therefore, it is required to introduce a dedicated module for on-line event building and feature extraction. The Central Controller Module, equipped with Xilinx Zynq SoC and 16 optical transceivers, serves as such true real time computing facility. Our solution for the continuous data recording (trigger-less) is a novel approach in such detector systems and assures that most of the information is preserved on the storage for further, high-level processing. Signal discrimination applies a unique method of using LVDS buffers located in the FPGA fabric.
number of pulisher's sheets:	0,3
affiliation:	Wydział Fizyki, Astronomii i Informatyki Stosowanej : Instytut Fizyki im. Mariana Smoluchowskiego, Wydział Fizyki, Astronomii i Informatyki Stosowanej : Zakład Technologii Gier, Wydział Fizyki, Astronomii i Informatyki Stosowanej : Zakład Technologii Informatycznych
type:	journal article
subtype:	academic paper