Investigating the Dirac operator evaluation with FPGAs

2019
journal article
article
dc.abstract.enIn recent years, computational capacity of single Field Programmable Gate Array (FPGA) devices as well as their versatility have increased significantly. Adding to that fact, the High Level Synthesis frameworks allowing to program such processors in a high-level language like C++, makes modern FPGA devices a serious candidate as building blocks of a general-purpose High Performance Computing solution. In this contribution we describe benchmarks which we performed using a kernel from the Lattice QCD code, a highly compute-demanding HPC academic code for elementary particle simulations on the newest device from Xilinx, the U250 accelerator card. We describe the architecture of our solution and benchmark its performance on a single FPGA device running in two modes: using either external or embedded memory. We discuss both approaches in detail and provide assessment for the necessary memory throughput and the minimal amount of resources needed to deliver optimal performance depending on the available hardware. Our considerations can be used as guidelines for estimating the performance of some larger, manynode systems.pl
dc.affiliationWydział Fizyki, Astronomii i Informatyki Stosowanej : Instytut Fizyki im. Mariana Smoluchowskiegopl
dc.affiliationWydział Fizyki, Astronomii i Informatyki Stosowanej : Zakład Technologii Informatycznychpl
dc.contributor.authorKorcyl, Grzegorz - 107362 pl
dc.contributor.authorKorcyl, Piotr - 125645 pl
dc.date.accessioned2019-09-03T12:36:44Z
dc.date.available2019-09-03T12:36:44Z
dc.date.issued2019pl
dc.date.openaccess0
dc.description.accesstimew momencie opublikowania
dc.description.number2pl
dc.description.physical56-63pl
dc.description.versionostateczna wersja wydawcy
dc.description.volume6pl
dc.identifier.doi10.14529/jsfi190204pl
dc.identifier.eissn2313-8734pl
dc.identifier.issn2409-6008pl
dc.identifier.projectROD UJ / OPpl
dc.identifier.urihttps://ruj.uj.edu.pl/xmlui/handle/item/81719
dc.languageengpl
dc.language.containerengpl
dc.rightsUdzielam licencji. Uznanie autorstwa - Użycie niekomercyjne 3.0*
dc.rights.licenceCC-BY-NC
dc.rights.urihttp://creativecommons.org/licenses/by-nc/3.0/legalcode*
dc.share.typeotwarte czasopismo
dc.subtypeArticlepl
dc.titleInvestigating the Dirac operator evaluation with FPGAspl
dc.title.journalSupercomputing Frontiers and Innovationspl
dc.typeJournalArticlepl
dspace.entity.typePublication
dc.abstract.enpl
In recent years, computational capacity of single Field Programmable Gate Array (FPGA) devices as well as their versatility have increased significantly. Adding to that fact, the High Level Synthesis frameworks allowing to program such processors in a high-level language like C++, makes modern FPGA devices a serious candidate as building blocks of a general-purpose High Performance Computing solution. In this contribution we describe benchmarks which we performed using a kernel from the Lattice QCD code, a highly compute-demanding HPC academic code for elementary particle simulations on the newest device from Xilinx, the U250 accelerator card. We describe the architecture of our solution and benchmark its performance on a single FPGA device running in two modes: using either external or embedded memory. We discuss both approaches in detail and provide assessment for the necessary memory throughput and the minimal amount of resources needed to deliver optimal performance depending on the available hardware. Our considerations can be used as guidelines for estimating the performance of some larger, manynode systems.
dc.affiliationpl
Wydział Fizyki, Astronomii i Informatyki Stosowanej : Instytut Fizyki im. Mariana Smoluchowskiego
dc.affiliationpl
Wydział Fizyki, Astronomii i Informatyki Stosowanej : Zakład Technologii Informatycznych
dc.contributor.authorpl
Korcyl, Grzegorz - 107362
dc.contributor.authorpl
Korcyl, Piotr - 125645
dc.date.accessioned
2019-09-03T12:36:44Z
dc.date.available
2019-09-03T12:36:44Z
dc.date.issuedpl
2019
dc.date.openaccess
0
dc.description.accesstime
w momencie opublikowania
dc.description.numberpl
2
dc.description.physicalpl
56-63
dc.description.version
ostateczna wersja wydawcy
dc.description.volumepl
6
dc.identifier.doipl
10.14529/jsfi190204
dc.identifier.eissnpl
2313-8734
dc.identifier.issnpl
2409-6008
dc.identifier.projectpl
ROD UJ / OP
dc.identifier.uri
https://ruj.uj.edu.pl/xmlui/handle/item/81719
dc.languagepl
eng
dc.language.containerpl
eng
dc.rights*
Udzielam licencji. Uznanie autorstwa - Użycie niekomercyjne 3.0
dc.rights.licence
CC-BY-NC
dc.rights.uri*
http://creativecommons.org/licenses/by-nc/3.0/legalcode
dc.share.type
otwarte czasopismo
dc.subtypepl
Article
dc.titlepl
Investigating the Dirac operator evaluation with FPGAs
dc.title.journalpl
Supercomputing Frontiers and Innovations
dc.typepl
JournalArticle
dspace.entity.type
Publication
Affiliations

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