Computer-aided 3D IC layout design task is computationally difficult and no deterministic polynomial time algorithms are able to solve it. The elaborated intelligent framework architecture for visual kind of design uses a simple shape grammar to generate topologically feasible solutions which are further optimized to meet design requirements. The search process is driven by an intelligent derivation controller that employs design specific knowledge given in a form of goals and constraints. The paper focuses on the post-generation 3D IC wirelength optimization stage. The original partitioning heuristics implemented by the means of the extremal optimization is applied to the MCNC set of benchmark circuits. The achieved results confirm the effectiveness of the proposed approach while applied to sparse circuits.